In order to obtain a sufficiently large read signal of the DRAM memory cell, the storage capacitor has to provide a sufficient storage capacitance. On account of the limited memory cell area, storage capacitors which utilize the third dimension are therefore used. One embodiment of such a three-dimensional storage capacitor is a so-called trench capacitor, which is arranged in a manner laterally adjoining the selection transistor, preferably essentially below the selection transistor, the inner capacitor electrode arranged in a trench being electrically conductively connected to the selection transistor. A further embodiment of a three-dimensional storage capacitor is the so-called stacked capacitor, which is likewise arranged in a manner laterally adjoining the selection transistor, preferably essentially above the selection transistor, the inner capacitor electrode being conductively connected to the selection transistor.
The selection transistor in the DRAM memory cell is generally a junction transistor in which two highly conductive doping regions are diffused into the semiconductor substrate and serve as current-supplying (source) and current-receiving (drain) electrodes, a current-conducting channel between source and drain electrodes being formed between the two doped regions with the aid of a gate electrode isolated by an insulating layer, in order to write and read the charge to and from the storage capacitor.
As the areas of the memory cells become smaller and smaller on account of increasing miniaturization, retaining the current driver capability of the transistor poses an increasing problem. Current driver capability of the transistor is understood to be the transistor's property of supplying, in the case of a predetermined source/drain potential and a predetermined gate voltage, a sufficient current in order to charge the storage capacitor sufficiently rapidly. However, the shrinking of the cell areas and the resultant shrinking of the transistor dimensions mean that the transistor width of the planar junction transistors decreases. This in turn has the effect of reducing the current switched through from the transistor to the storage capacitor. One possibility of retaining the current driver capability of the planar transistor with a reduced transistor width consists in correspondingly scaling the gate oxide thickness or the doping profile of the source/drain regions and of the channel region. However, there is the problem of increased leakage currents when the gate oxide thickness is reduced or the doping concentrations are higher.
As an alternative to planar DRAM selection transistors, therefore, vertically arranged transistors are increasingly being discussed in order, in the case of selection transistors, too, additionally to be able to utilize the third dimension and obtain larger transistor widths. In the case of such a vertical selection transistor, which, in the case of an assigned trench capacitor, is arranged essentially directly over the trench capacitor and, in the case of an assigned stacked capacitor, is arranged essentially directly under the stacked capacitor, there is, in particular, the possibility of enclosing the channel region of the transistor almost completely with the gate electrode, as a result of which the current driver capability per transistor area can be significantly increased. However, vertically embodied transistors are very complicated in terms of process engineering and can be fabricated only with difficulty, in particular with regard to the connection technique of the source/drain regions and of the gate electrodes of the transistor. What is more, there is the problem that, during the operations of switching the selection transistor on and off, the semiconductor substrate is also concomitantly charged at the same time, and the so-called floating body effect occurs, as a result of which the switching speed of the transistor is greatly impaired. In order to prevent this, the semiconductor substrate is generally provided with a substrate connection in order to ensure that the semiconductor substrate is discharged during the transistor switching operations. In the case of vertical selection transistors, however, there is the problem that even with the aid of such substrate connections, the semiconductor substrate can often be discharged only to an inadequate extent.
Furthermore, in particular in connection with logic circuits, new junction transistor concepts are known which can achieve a higher current intensity relative to the transistor width in comparison with the conventionally planar transistors. One possible short-channel junction transistor concept is the so-called double gate transistor, in which the channel region between source and drain regions is encompassed by a gate electrode at least on two sides, whereby a high current driver capability can be achieved even in the case of very short channel lengths since an increased channel width results in comparison with conventional planar selection transistors. In this case, it is preferred for the double gate transistor to be designed as a so-called Fin-FET, in which the channel region is embodied in the form of a fin between the source and drain regions, the channel region being encompassed by the gate electrode at least at the two opposite sides. Given a suitable design of the fin width and thus of the channel width, such a Fin-FET can be operated in such a way that, in the turned-on state with an applied gate electrode voltage, the two inversion layers that form under the gate electrodes overlap and a complete charge carrier inversion thus takes place, as a result of which the entire channel width can be utilized for current transport. What is more, Fin-FETs afford the possibility of directly controlling the so-called short-channel effects, which occur in the case of very short channel lengths and may lead to an alteration of the threshold voltage of the transistor, by means of the gate potential instead of, as in the case of conventional planar FETs, through the need to provide special doping profiles in the channel region of the transistor. An improved control of the short-channel effects is thus achieved with the aid of the Fin-FET. Furthermore, Fin-FETs are distinguished by a large subthreshold gradient and thus a good switch-on and switch-off behavior in conjunction with a reduced subthreshold leakage current. Not having to control short-channel effects by means of the channel doping additionally makes it possible to reduce the channel doping and thus to achieve a high channel mobility and a high threshold voltage.
Double gate transistors, in particular Fin-FETs, are generally fabricated on an SOI substrate (SOI=silicon on insulator) in order to avoid impairing the electrical properties of the double gate transistors. In the case of an SOI substrate, the silicon layer in which the transistor is formed is isolated from the underlying semiconductor wafer by a buried insulator layer. This configuration has the disadvantage that when the double gate transistor is intended to be used as a selection transistor for a DRAM cell, the silicon layer is charged as a result of the transistor being switched on and off, which significantly impairs the switching speed of the transistor. Although it is possible to avoid such charging of the silicon layer with the Fin-FET by means of an additional electrical connection, said additional connection can be effected only directly via the silicon surface, which results in an increased area requirement on account of the additional connection area, which is at odds with the desired miniaturization of the DRAM memory cell.